Architectural design of an RISC processor for programmable logic controllers

In this paper, an architecture of the RISC processor for pro-grammable logic controllers is proposed. Execution characteristics of relay ladder logic, the most common language of PLCs, are analyzed with various application programs. A conditional execution mechanism is developed to prevent pipeline hazards caused by the inherent execution behaviour of relay ladder logic. The instruction sets of three diierent architectural models are deened. Translators, assemblers, and simulators for three models are developed to evaluate the performance and to choose an optimal architecture for programmable logic controllers. The proposed processor, which has accumulator architecture with a four-stage pipeline, exhibits desirable performance much higher than that of recent commercial PLCs.